Faster and efficient packaging is crucial for IC design and manufacturing.
From IC design to production, the race for creating new silicon is constantly operating at breakneck speeds. Companies, especially those in the computer industry, are always looking for new edges to reduce cost, size, and power consumption. At the same time, new designs incorporate more features in the new chipsets. That’s why OEMs are constantly increasing their teams of design engineers to create highly customized silicon.
Once the initial design is complete, and simulations provide the results expected, packaging the ICs is the next crucial step to production. The demand for post-GDSII backend services has increased exponentially across all applications. Additionally, Hypercalers and OEM companies face technical challenges and limitations on traditional backend services.
Hypescalers and OEMs are relying more on front-end IC design
Over the past 20 years, there has been a continuous trend to move more applications and data to the cloud. Additionally, new technologies such as the Internet of Things (IoT) have exploded, and now we have billions of devices connected to the internet.
Furthermore, automotive system complexity continues to rise with the use of high-performance system-on-chips (SoCs) to deliver innovative applications and features, such as electrification, ADAS, and V2X connectivity.
Those developments are responsible for the sudden expansion of new integrated silicon to address the increased need for speed and reduced size and power consumption.
Many top cloud computing companies constantly upgrade their high-performance computers with new, more efficient processors and other devices.
Additionally, OEMs producing IoT devices are designing and sourcing new integrated chipsets to save power, board real estate, and reduce their component count. A new wave of highly integrated SoCs is already in the market, and new chipsets are rolling out daily.
Companies are outsourcing packaging, testing, and production to specialized ASIC companies in strategic areas
Most hypercalers and OEMs do not have the in-house resources for tape-out, packaging, testing, and production of the chipsets. That’s why they reach out to specialized ASIC companies to assist them in the final stages of the chipset’s production process.
Sophisticated high-performance front-end design resources are expensive and depending on geographic location, they can be scarce too. The result is an uptick in companies outsourcing packaging, testing, and production responsibilities to ASIC companies with experience in these strategic areas.
“The hyperscalers today are investing heavily in upfront design to create differentiation. As a result, they’re looking for ASIC companies that can provide the backend capabilities to maximize their investment in differentiated front-end design with equally innovative backend differentiation. These once-pedestrian practices are now highly prized for wringing out every last bit of performance power and area,” says Johnny Shen, Alchip Technologies’ President & CEO.
Alchip has seen an exponential increase in post-GDSII assignments across all high-performance ASIC applications
Over the past nine months, the company has seen an exponential increase in these post-GDSII assignments across all high-performance computing ASIC applications. The company’s most recent activity has driven a track record of over 450 backend tape-outs and billions of devices now coming out of production.
Alchip’s APE capabilities
Alchip’s new advanced package engineering (APE) capabilities now include Chip-on-Wafer-on-Substrate (CoWoS®). The company also expects to offer InFO capability in late 2021.
The CoWoS process offered by Alchip runs on dedicated tooling and can show the IP performance equivalent to the original design. The process also includes online debugging and active thermal control. The company’s in-house substrate design and test capabilities assure compliance with all system requirements and establish the framework for critical foundry-to-final test flow.
To secure the requisite quality for complete physical designs, the company implements two sign-off verification options to accommodate design economics and enhanced yield objectives. The standard sign-off verification option includes DRC/LVS/ERC checks that guard against fatal manufacturing errors. A second design option calls for additional focus on Electrical, DFT, STA, and/or clock verification, depending on specific customer requirements.
“Our key to success is knowing how to target advanced technology so that we can collaborate with the customers to develop a manufacturing protocol that is done ‘their way’ rather than one monolithic approach that is done our way,” explains Mr. Shen.