Heterogeneous Integration Needs Tools, Models
Semiconductor industry researchers have for years been looking at alternative approaches to help satisfy the relentless drive for more intelligence, more connectivity, more computing power and higher bandwidth — without pushing costs sky high.
Heterogeneous integration (HI) — separately manufactured silicon and non-silicon components integrated into a higher level system in the same three-dimensional system-in-package — has increasingly garnered attention from researchers and chip firms as the way of the future for achieving high-performance computing and higher bandwidths attainable without having continuously pushing the envelope of Moore’s Law scaling. An IEEE-backed effort to create a pre-competitive technology roadmap outlining a long term vision for HI and identify challenges and potential solutions has been underway since 2016.
At the SEMI 3D & Systems Summit here last week, Guido Uberreiter, Globalfoundries’ vice president of pre- and postfab operations, told an audience that the race for smaller process technologies was not necessary for every element of a system.
“Ten years ago, it was all about getting more transistors on silicon,” Uberreiter said. “But with costs rising — especially for 5nm and 7nm — not all devices need all that performance.”
He added that while the concept of Moore’s Law might be nearing the end for 2D semiconductors, it’s alive and well with 3D stacking. “You can do RF and CMOS on one chip and the photonics on the board, for example,” Uberreiter said.
While heterogeneous integration in semiconductor packaging has been around for a while and is actually well advanced in some areas, realizing the industry’s vision for HI will require tools for automating system partitioning and design in the same way that EDA tools made it easier to design application specific ICs more than 30 years ago.
The HI approach enables system technology co-optimization and is analogous to the evolution of multichip modules in the 1990s, said another speaker at the conference, Eric Beyne, an imec fellow.
“One size does not fit all — single chip, single technology implementation in system-on-chip (SoC) doesn’t cut it anymore,” Beyne said.
Like other speakers, Beyne outlined how 3D system partitioning can be used to separate out different functions, such as logic, memory, analog, RF, power, detectors and displays. The most advanced technologies can be used for the most performance critical, but other layers can house functional blocks that don’t need the latest process node, he said. The layers can be stacked, and because they are specialized for a specific function, the chip can be made more cost-effective, he added.
Particularly in the age of IoT, proponents see HI lending itself to distributed embedded intelligence, with high performance and lower power consumption, essentially to handle all the data that’s being generated.
“Cognitive sensing will be very important to reduce the amount of data being sent to the cloud,” said Hubert Lakner, a professor and director at the Fraunhofer Institute for Photonic Microsystems. “In other words, we need to interpret the data locally. We need to analyze the big data to make it smart data.”
Lakner also highlighted the power consumption aspect. “It can typically require 15kW just for computing the data in an autonomous car for example,” he said. He concluded that HI would be the only currently available process to achieve the necessary complexity in future systems.
Addressing higher bandwidth can also be achieved with advanced packaging. Ravi Mahajan, an Intel fellow, talked about the benefits of integration on package as the next step beyond integration on silicon.
Like others at the conference, Mahajan highlighted the modular approach being driven by various researchers and Darpa’s CHIPS program, which proposes a system-in-package CAD flow for dense interconnects and high-performance computing, as well as pre-validated chiplets and new business models.
The chiplet approach like building with Lego blocks, as several speakers highlighted at the conference. Pascal Vivet, scientific advisor at CEA-Leti, said it’s possible to envisage, for example buying a chiplet from a company like Arm.
“The world will move from IP suppliers to chiplet suppliers,” Vivet said, adding that this will require the advent of methods for integrated testing of chiplets and new the evolution of new business models to enable suppliers to offer modular hardened blocks in the same way as IP vendors do today.
“But for someone who could do it [sell chiplets], there’s a lot of money to be made,” he said.
Intel’s Mahajan mentioned Intel’s new Foveros packaging technology — introduced in December — which uses 3D stacking to enable logic-on-logic integration. Foveros is expected to extend die stacking beyond traditional passive interposers and stacked memory to high-performance logic, such as CPU, graphics and AI processors. It will allow products to be broken up into smaller chiplets, where I/O, SRAM and power delivery circuits can be fabricated in a base die with high-performance logic chiplets stacked on top.
Utilizing such a structure can enable Intel to combine a high-performance 10nm compute-stacked chiplet with a low-power 22FFL base die, enabling both performance and power efficiency in a small form factor, Mahajan said.
While the use of chiplets is being advanced by companies like Intel and Marvell, as well as imec, one of the big challenges will be the EDA considerations. Imec’s Beyne said new EDA tools will be required for things like simultaneous 3D placement of cells on the various tiers and automated partitioning. He said companies like Cadence and Synopsys are exploring such tools for SoC partitioning.
Connecting the chiplets or stacks was also a key topic at the conference — particularly the different options like interposers and silicon bridges. Romain Fraux, CEO of System Plus Consulting, outlined the techniques and the benefits of each, and said that Intel’s silicon bridge makes a significant difference in terms of silicon size compared to the interposer used by others.
Fraux highlighted the latest generation of Apple and Samsung watches as examples of highly integrated systems in package, albeit with differing processes.
The Apple Watch series 4 is an example of a highly integrated system-in-package, with 30 ICs and many passives on one side. Since 2015, Apple has released five different generations of smartwatches. Each generation was built around an SiP integrating all the components from the application processor to the power management integrated circuit (PMIC).
In the second generation, the SiP used single-side molding technology. The third generation brought Long Term Evolution (LTE) standard wireless communication through additional components soldered beneath the SiP. In the fourth generation, several supplying companies have integrated their latest advanced packaging technology in order to offer the smallest and most integrated SiIP since the beginning of the Apple Watch series.
The Series 4 smartwatch has two versions of the SiP. One is a non-cellular version, with single side molding and an inertial measurement unit (IMU) and a GPS front-end module (FEM) soldered beneath the package. The second is the cellular version with additional radio frequency (RF) FEM, inside and outside the SIP, and a baseband processor included in the packaging, all in a single package smaller than 700 mm², representing 40% of the watch’s form factor.
Since the first generation, the system has used packaging technology from ASE to form the SiP, featuring internal shielding isolating the RF area from the other components. In this generation, Apple chose TSMC to provide the application processor packaging with its latest integrated fan-out (inFO) technology, called inFO-ePoP. Apple has also used two more advanced packaging technologies to integrate a PMIC and an RF FEM in such a small form factor. The first uses embedded die technology, coupling several passives on a printed circuit board (PCB), and the IC soldered beneath. The second uses double-sided ball grid array (BGA) technology to integrate a switch at the bottom of an SiP including several filters and power amplifiers.
The Samsung Galaxy Watch was the first in the industry to use large size panels dedicated to IC assembly, moving fan-out package manufacturing from wafer (FOWLP) to large scale panel (FOPLP). Developed by Samsung Electro Mechanics (SEMCO), it is clearly targeting TSMC’s leadership in high-density fan-out packaging, with an aggressive roadmap for FOPLP technology development.
With the growth of demand for small size and slim z-height packaging, SEMCO adopted a newly developed FOPLP-based solution, in direct competition with inFo from TSMC. Using this technology, the Galaxy Watch from Samsung features a combination of a PMIC with an application processor unit and a DRAM in the same package, called SiP -ePoP. PMIC and APE are placed side by side in an embedded structure that realized the top/bottom connection in the packaging. This approach could drastically reduce the packaging cost. Besides the cost advantage, SEMCO managed to get a line/space around 10 micron, a dimension that is comparable to TSMC’s InFo technology.