RISC-V Chiplet Startup Raises $38m, Targets Data Center Compute
Ventana Micro Systems, a RISC-V startup headquartered in Cupertino, CA, has emerged from stealth announcing $38 million in funding and revealing details of its multi-core system-on-chip (SoC) chiplet targeting data center compute.
Established in 2018, Ventana’s offers RISC-V CPUs with extensible instruction set capability delivered in the form of multi-core chiplets. It also offers a customizable SoC chiplet that hyperscalers could adopt to get a head start on their own product designs, rather than take a few years to develop their own custom processors.
Ventana said its compute chiplets are designed to deliver best-in-class single thread performance optimized for cloud, enterprise data center, 5G, edge compute and automotive applications. This is a result of its microarchitectural innovation which makes the design highly portable across different fabs and process nodes.
On paper, the press announcement sounded fanciful, so EE Times spoke to one of the founders, Balaji Baktha, to get some more background and it became clear this was more than just another RISC-V project. He and his co-founder and Greg Favor both have a strong track record in data centers, CPU architectures and network processors. Baktha emphasized his work on several generations of data centers, with companies like Marvell, Adaptec, and Veloce Technologies; and Favor’s work with successful server class x86, Arm 64-bit CPUs and network processors, through key roles at AMD, Ampere, Sierra Systems, and Montalvo.
Baktha explained, “Over the years, we learned a lot about hyperscalers, so our team’s capabilities exceed many others in addressing this area. Our core team has been together at firms like AMD and Veloce Technologies for over 20 years and have seen the limitations of existing architectures. Hence our founding vision was clear: to deliver standalone data center class processors.”
He said, “Nearly half of compute spend is moving away from general purpose processors in favor of infrastructure compute and domain specific accelerators. Ventana is perfectly positioned to capitalize on this trend with our high-performance cores built on the extensible RISC-V architecture, and our chiplet-based rapid productization approach.”
In addition to their own track record, Ventana also has prominent investors behind it who believe its new approach could be “revolutionary.” This series B round led by Marvell founders Sehat Sutardja and Weili Daiits takes its total funding to date to $53 million, with other unnamed semiconductor industry investors (however, SEC filings indicate directors with strong background in system architecture at Cisco and MIPS).
Sehat Sutardja commented, “Ventana’s high-performance solutions have the potential to reshape silicon design as we know it, making it possible for companies to develop super powerful solutions in record time and without an extensive budget. We believe this approach to be revolutionary in several growth markets including data center, 5G, automotive, enterprise and client computing.”
Part of Ventana’s work while in stealth mode was to work with key players to validate its solution, and Cisco was an important partner in this process. Baktha said, “They took our architecture and put it through validation. Getting Cisco on board helped us raise our series A funding of $15 million.” Providing that support, Eyal Dagan, executive vice president of the common hardware group at Cisco Systems, said, “Ventana has created an innovative RISC-V architecture that addresses the market need for a high-performance, customizable and secure processor solution.”
Linley Gwennap, principal analyst at The Linley Group, also thinks the chiplet strategy is an appropriate next step. He said, “As Moore’s Law is slowing, the industry is moving towards chiplet-based designs that optimize cost by using the right process node for each component of the design. Ventana’s chiplet strategy accelerates deployment of this emerging approach across a broad range of customers and partners while tapping rising adoption of the open-source RISC-V architecture.”
Ventana said its modular, scalable chiplet-based product strategy enables significant reduction in development time and cost compared to the prevailing intellectual property (IP) model. While Ventana’s compute chiplets maximize performance by targeting cutting edge process geometries, customers can implement their unique SoC chiplet silicon in the most optimal process node for the target application. To ensure interoperability, Ventana offers a parallel die-to-die (D2D) solution capable of very low latencies, high bandwidth and lowest power. The D2D solution is compliant with the OCP Open Domain-Specific Architecture (ODSA) physical interface standard.
Baktha said, “By providing this chiplet IP and standards-based SoC connectivity, we are enabling the ultimate server disaggregation play. This is only truly possible when compute and memory can scale independently. For the first time, an accelerator can be cache coherent.” He added that Ventana’s chiplet approach means hyperscalers can save in the order of $20 million in costs and cut two years of the development time compared to the prevailing IP model, and as a result the company is already working with the key hyperscalers. The company hopes to tape out a chip next year.