Unpatterned wafer inspection, which has flown well under the radar for most of the semiconductor industry, is becoming more critical amid the need to find defects earlier in the manufacturing process flow.
Finding those defects is getting harder as critical dimensions shrink. It’s more difficult to actually detect smaller defects on bare wafers, there is more data to process, and there is more pressure to process and inspect more quickly. And while there are solutions to all of these problems, there is a cost associated with each of them.
Generally, wafer inspection is split into two categories—unpatterned and patterned. In simple terms, unpatterned wafer inspection looks for defects on unprocessed or bare silicon wafers. Patterned inspection detects defects on processed wafers. Hitachi High-Technologies, KLA-Tencor, Rudolph and others compete in the unpatterned wafer inspection equipment market in one form or another.
Unpatterned wafer inspection tools are used in various parts of the IC production flow, including the initial stages of the semiconductor process. In the early stages, silicon wafer makers produce and sell bare or unprocessed silicon wafers to chipmakers, who process them into chips in the fab.
Fig. 1. Silicon wafers. Source: Nanografi Nano Technology
But before silicon wafer makers ship the substrates to chipmakers, the bare wafers must have few or no defects. Intrinsic defects on bare wafers eventually can lead to killer defects on the final chips.
That’s where unpatterned wafer inspection fits in. The goal of these systems is to find defects on bare wafers at high throughputs with reasonable costs. “We want to find the defects early in the game. These defects, either on a substrate or on a film, get created and become bigger. And finally, they get to be a problem down in the line,” said Jijen Vazhaeparambil, vice president and general manager of the Surfscan-ADE division at KLA-Tencor.
Then, once the bare wafers meet spec, they are shipped to the fab for processing. In the fab, the processed wafers eventually are inspected for defects using a different set of equipment called patterned wafer inspection. As before, patterned wafer inspection is also important, as these tools locate killer defects on the wafer in the fab.
Over the years, there have been tomes written about patterned wafer inspection. In contrast, unpatterned wafer inspection is less understood, but the technology is also critical. Unpatterned wafer inspection is used for all types of devices, such as those with III-V materials, analog, logic and memory.
In 2017, the unpatterned wafer inspection market was a $439 million business, according to Gartner. “This market has grown well in the past few years due to the increased use of these tools in 3D NAND production,” said Bob Johnson, an analyst with Gartner.
In 2017, KLA-Tencor was the leader in the market with $404 million in sales, or a 92% share of the business, according to Gartner. Hitachi High-Technologies was the only other major player with about $25 million in sales, according to the firm.
Booming wafer demand
For years, the industry has used unpatterned wafer inspection tools for several applications, such as tool monitoring, process monitoring and unpatterned wafer quality control.
Tool and process monitoring are related. In both cases, chipmakers often want to check on the health or cleanliness of a tool or tools in the fab. Tool/process monitoring can be conducted before and during the production phase in the fab.
For this, chipmakers run unprocessed or dummy bare wafers through the equipment. Then, they will put the bare wafer in an unpatterned wafer inspection system, which will then detect the particle counts of the tool and determine if the system causes defects.
Equipment vendors also use unpatterned wafer inspection for similar reasons. Tool vendors can determine whether a given system is creating defects during processing.
In addition, silicon wafer makers use unpatterned wafer inspection to inspect bare silicon wafers. Chipmakers also use these tools for incoming inspection of bare wafers into the fab.
Silicon wafers are a fundamental part of the semiconductor business. Every chipmaker needs to buy them in one size or another. Silicon wafer makers produce substrates with diameters of 300mm, 200mm and smaller.
Several dynamics are at play in the silicon wafer business, including the supply/demand picture and technology challenges. On the demand front, the silicon wafer industry suffered for several years, due to oversupply and falling prices. There were simply too many suppliers and capacity in the market.
Then, starting in 2016, the silicon wafer industry began to consolidate. And last year, silicon wafer vendors experienced tight supply amid booming demand. Many even raised their prices.
“The silicon wafer industry experienced several years of declining ASPs [average selling prices], but the overall shipments continued to grow,” said Clark Tseng, director of industry research and statistics at SEMI. “In 2017, we saw a rebound in the ASPs, which contributed to a 17% revenue growth.”
In the first half of 2018, the market was robust. In fact, in Q2 the market reached its highest recorded quarterly level in history, as worldwide silicon wafer area shipments rose 2.5% to 3,160 million square inches from 3,084 million square inches the previous quarter, according to the SEMI Silicon Manufacturers Group. New quarterly total area shipments were 6.1% higher than second quarter 2017 shipments.
Going forward, the supply of silicon wafers is expected to remain tight for some time. “Long term, the capacity for silicon wafers has been pretty much fully booked until 2020. Most of the big customers are looking for long-term contracts beyond 2020. We see some potential of capacity growth next year and into 2020, as well,” Tseng said.
Table 1. Growth of worldwide silicon wafer market. Source: SEMI
Demand is strong for 300mm silicon wafers, but there is also a surge in the 200mm arena. “200mm fabs worldwide are gearing up to add more than 600,000 wafers per month from 2017 through 2022, an 11% growth rate that will lead to a new high of 6 million wafers per month by the end of 2022,” said Christian Dieseldorff, an analyst with SEMI, in a blog.
Besides the demand picture, there are also some technology challenges in the silicon wafer business. In the silicon wafer production flow itself, the process starts with polysilicon. Polysilicon is melted in a quartz crucible along with electrically active elements.
A silicon seed crystal is lowered into the crucible. The resulting body is called an ingot, which is pulled and sliced into monocrystalline wafers. The sizes vary, depending on the requirements.
Fig. 3. Silicon wafer process flow. Source: GlobalWafers
It’s critical to make silicon wafers that are flat and particle-free, so that defects are not incorporated into the final chip. But at times, crystallographic defects are generated during the silicon ingot growth process and subsequent steps. On bare wafers, there are several types of defects, such as simple particles, crystal originated particles or pits (COPs), residues and scratches.
“The challenge of advanced wafer technology from my perspective is fewer defects. Controlling defects in the bulk crystal is always a challenge as well as consistency of specs edge-to-edge. As substrates become larger, it is more likely that there will be a chance of defects,” said John Syring, senior sales and process engineer with Linton Crystal Technologies, a supplier of Czochralski process crystal growing equipment for use in producing monocrystalline ingots.
There are solutions to the problem. “This is the primary reason that the use of superconducting magnets are being used for 300mm crystal growth. The magnet helps stabilize the melt to provide a more uniform growth condition with more consistency across the surface of the wafer,” Syring said.
Still, defects and COPs may crop up during the process. New types of materials may also create defects. And then, the process may cause unwanted roughness on the wafer surface.
Needless to say, it’s critical to find defects before these bare wafers reach the fab. In some cases, these imperfect wafers can be cleaned or reworked at the silicon wafer house to meet spec. Wafers that can’t meet spec get rejected.
Regardless, it’s imperative to use unpatterned wafer inspection, but the challenges are growing for 300mm silicon wafers at advanced nodes. “The challenges associated with unpatterned wafer inspection include the detection of even smaller defects on the wafer surface and inside the wafer volume,” said Felix Moellmann, a systems engineer at Rudolph Technologies. “Increasing requirements to detect and classify defects like pits and slip lines add challenges and complexity to the inspection process.”
There are other challenges. “The biggest challenge for unpatterned wafer inspection is sensitivity. At advanced design nodes, higher pattern density and smaller critical dimensions shrink the minimum size of a yield-killing defect on bare silicon wafers or blanket-film monitor wafers. In determining necessary sensitivity for a particular process step, however, it’s important to understand how defects evolve through different process steps,” KLA-Tencor’s Vazhaeparambil said.
Then, of course, the industry wants to inspect defects with a reasonable cost-of-ownership. “High-sensitivity inspection becomes more important, because of miniaturization and reliability of devices. Low inspection cost is also required as well as high-sensitivity. In order to satisfy customer requirements, it is necessary to achieve both high-sensitivity and high-throughput,” said Naohisa Sekoguchi, manager of optical inspection at Hitachi High-Technologies.
On top of that, there are various challenges with the different silicon wafer types. In chip production, the industry uses the following wafer types—anneal, epitaxial, polished and SOI.
Epitaxial wafers, which consist of a monocrystalline silicon layer grown on the substrate, are used for microprocessors, image sensors and power devices. “Epi wafers are well addressed with today’s inspection equipment. But epi wafers present a challenge in terms of various occurring and controlled patterns that must be measured and classified, leading to efforts in machine vision,” Rudolph’s Moellmann said.
Polished wafers are used for DRAM and NAND flash. These require ultrapure substrates with flat and clean surfaces. In the inspection process, polished wafers are more of a challenge, as pits and other defects tend to appear during the bulk crystal growth process.
Annealed-based wafers also are gaining steam. In the anneal process, a batch of polished wafers are placed in a furnace and heated.
Silicon-on-insulator (SOI) wafers are different. An SOI wafer incorporates a thin insulating layer in the substrate as a means to suppress leakage. The thickness of the insulating layer, or buried oxide layer, is roughly 20nm to 25nm.
Soitec, the world’s largest supplier of SOI substrates, performs unpatterned wafer inspection at its production sites. “Surface (frontside, backside and edge) quality, geometry and edge roll-off are the key parameters for SOI quality,” said Christophe Girard, product engineering director at Soitec.
For SOI wafers, there are some inspection challenges. “The challenge for inspection is to detect and classify any kind of shallow or smooth abnormality at the surface,” Girard said. “Top silicon and buried oxide thicknesses as well as surface roughness can affect reflectivity, creating challenges for detection.”
Today, the industry is ramping up devices based on FD-SOI substrates. Typically, FD-SOI products have a low surface roughness and are measured at the same low threshold as polished or epi wafers. “Complexity will increase for thinner SOI layers (typically less than 5nm) or more complex stacks integrating SiGe or III-V materials,” he added.
Fig. 3 FD-SOI substrate. Source: Soitec
Fortunately, there are solutions in the unpatterned inspection market. Hitachi High-Technologies, KLA-Tencor and others are taking slightly different approaches to solve the challenges in the market.
In the latest systems, tool vendors are using advanced light sources, sensors and software to find defects. Then, tool vendors must process more data than ever. In some cases, they are using machine learning techniques to find and classify defects.
In the latest announcement, KLA-Tencor recently rolled out a new unpatterned inspection system. The tool, dubbed the Surfscan SP7, is targeted for 10nm/7nm and advanced memory. The sensitivity for the tool is 15nm, compared to 19nm for the previous model.
Like the previous system, the SP7 is based on a 266nm deep-ultraviolet (DUV) light source. But the latest system incorporates a new, low-noise CCD sensor. This enables the detection and classification of various defect types, such as particles, scratches, slip lines and stacking faults. It can also inspect thin EUV photoresist materials on a surface.
Besides finding defects, KLA-Tencor and others must also deal with another issue—the explosion of data in the fab, particularly in inspection.
“It’s not just about defects. It also requires much more computing algorithms. Our tool collects an enormous amount of data. There is no shortage of data. But (the challenge) is how do you turn around the data really fast, mostly in real time, which you can react to on-the-fly,” KLA-Tencor’s Vazhaeparambil said.
Others agreed. “The need to inspect all surfaces, including the notch, will become increasingly important,” Rudolph’s Moellmann said. “An additional future challenge will be the precise categorization of defects using automated defect classification. The volume of data and the increased number of defects will call for AI-enhanced defect processing.”
In this case, unpatterned and patterned wafer inspection are moving in the same direction. Both require new machine learning techniques for fast defect detection and classification.
Needless to say, capturing defects is key in both the silicon wafer house and the fab. In fact, it’s more critical than ever.