Different materials, approaches for contacts and interconnects begin to surface for 7/5nm.
Chipmakers are moving ahead with transistor scaling at advanced nodes, but it’s becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes.
A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The transistor resides on the bottom of the structure and serves as a switch. The interconnects, which reside on the top of the transistor, consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another. Those interconnects are becoming more compact at each node, causing an unwanted resistance-capacitance (RC) delay in chips.
Compounding the issues is a relativity new layer called the middle-of-line (MOL). The MOL connects the separate transistor and interconnect pieces using a series of contact structures.
Both the contacts and interconnects play a big role in transistor and circuit performance. “As scaling continues to 10nm and below, contact and interconnect resistance is skyrocketing and is becoming the key limiting factor for device performance,” said Yang Pan, CTO for the Global Products Group at Lam Research. “At the same time, the reliability requirements, such as electromigration, are becoming more challenging.”
Fabricating the interconnects is difficult in the fab, although the MOL contacts are fast becoming one of the bigger challenges in device scaling. For example, GlobalFoundries recently conducted a review of its new 7nm finFET technology. “If I look at the list, there are 30 elements that we are working on to boost the performance,” said Gary Patton, chief technology officer at GlobalFoundries. “I would say the vast majority of those are all around the middle-of-line RCs in terms of taking the resistances and capacitances down. So there is a lot of optimization around the middle-of-line.”
Until very recently the industry was making little progress on this front, but new solutions are beginning to emerge. For example, the MOL contacts may migrate from traditional tungsten materials to cobalt, which reduces the line resistance in chips.
Longer term, the industry is working on a replacement for copper as the metallization scheme for advanced logic interconnects. Cobalt is emerging as a replacement material there, as well, at least for some layers. And finally, chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, which could help simplify the contact and interconnect process flows.
Clearly, foundry customers need to keep a close eye on these developments. IC designers have the ability to design chips around a wide range of wiring schemes and interconnect stacks, although there are potentially more restrictions at each node. EUV, cobalt and other technologies won’t solve every problem, but they are steps in the right direction.
What is MOL/BEOL?
Chipmakers are shipping 16nm/14nm finFET processes, with 10nm and 7nm either ramping or just around the corner. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.
Not all will move to 16nm/14nm and beyond, however. For many, it’s too expensive or not required. Rather than pushing to the next node, they plan to stick with planar processes at 28nm and above.
Others, meanwhile, will opt to go vertical rather than brute-force scaling. “There is an increasing interest for 2.5D and through-silicon via (TSV) technology,” said Chih Chien Liu, deputy division director for UMC’sadvanced technology development Module Division.
Companies that do make the move to 16nm/14nm and beyond will encounter several new and expensive process steps at the front-end-of-the-line (FEOL), MOL, and backend-of-the-line (BEOL). Transistors are manufactured in the FEOL in a fab. Contacts and interconnects are made in the BEOL in the fab.
In the MOL/BEOL, for example, there are new lithography, etch and gap-fill steps, Liu said. “At 10nm/7nm, self-aligned quadruple patterning (SAQP) or EUV will be applied for further dimensional scaling in the BEOL.”
Both the MOL and BEOL have their own challenges. “The backend-of-the-line is not getting any easier,” said David Fried, chief technology officer at Coventor. “It doesn’t quite have the same topological challenges as the middle-of-line, but you need to repeat the process over and over again. The middle-of-line interconnect is the battleground right now. It has the dimensional constraints of both the front-end and backend. It has the design freedom that neither the front-end or backend have, so there are more shapes and constructs to manage than anything else.”
In a simple process flow, a chipmaker first develops a finFET transistor with fins and a gate. A source and a drain are formed on each end of a fin.
From here chipmakers have different flows. In some cases the MOL process starts after the finFET formation. Chipmakers may split the MOL into two layers, lower and upper. Others may have one layer, depending on the design. For a two-layer scheme, both layers consist of tiny contacts, which are basically three-dimensional structures with a small gap. Using a deposition process, the gap within the contact is filled with tungsten, which is conductive.
In the lower MOL layer an interface material—nickel silicide—is deposited on the source, drain and gate. Then contacts are formed on top of these structures. The contacts are based on a titanium-titanium nitride-tungsten scheme. The first level or layer is sometimes called the contact-to-active or the trench silicide.
“The first contact is the contact to the junction. That’s where the low-resistance Schottky barrier and the silicides reside,” said Keyvan Kashefi, global product manager at Applied Materials. “For the first layer, we still need the Ti for the TiSi formation, and we need TiN as capping layer on Ti to prevent oxidation.”
On top of that is the second layer, where you are making contact with the bottom layer. For this, the next step is to make a contact called a tungsten plug on the second layer. To do that, a nitride/oxide layer is deposited on the finished finFET structure. Then contact holes are patterned on that layer using 193nm lithography and multiple patterning.
The holes are then etched and filled with tungsten. The tungsten plug is sandwiched between a liner material (titanium) and a barrier layer (titanium nitride).
At each node, though, this contact is becoming smaller. At 16nm/14nm, the critical dimension (CD) of the contact is approximately 25nm. At 10nm, the CDs of the contact are expected to range from 10nm to 15nm.
So the volume of the tungsten conductor material decreases at each node, meaning a signal must flow through a smaller amount of conductive metal. This, in turn, causes a big problem—contact resistance.
Looking to solve that problem, Applied Materials recently devised a new plasma-enhanced chemical vapor deposition (PECVD) process. This enables a metal-organic tungsten film, which is capable of replacing the thicker barrier layer.
In effect, the new film reduces the overall liner/barrier thickness. This helps increase the volume of the tungsten in the plug, thereby lowering the contact resistance. “The tungsten liner that we introduced was on the upper levels of the contact. It was not used at the junction or the contact to the silicide,” Kashefi said. “We are successfully able to demonstrate that on the upper levels of the contact. If you can reduce the thickness of the liner and barrier, and displace it with a more conductive metal, you can see significant reductions in the contact resistance as it relates to the plug resistance.”
While the metal-organic tungsten film addresses the upper layers, there are still issues with the lower MOL contact layers in terms of resistance. “The question now is what can we do at the junction area? That one is becoming the bottleneck,” Kashefi said.
To solve this issue, the contact will likely migrate from tungsten to cobalt materials at 7nm or so. “For contacts, we are moving to a cobalt fill process,” he said. “The cobalt fill is currently for the contact trench silicide and possibly the plug.”
Cobalt has several advantages. It doesn’t require nucleation layers, which provides more room for bulk metal. And cobalt enables high-aspect ratio features and void-free seamless fills.
Meanwhile, at the recent IEDM conference, the team of GlobalFoundries, IBM and Samsung presented a paper that provided some clues on the future directions of both the MOL and BEOL. The IEDM paper itself describes the development of a 7nm finFET technology with a contact poly pitch of 44nm/48nm and metallization pitch of 36nm.
The fins were pattered using SAQP. In contrast, EUV was used to pattern the MOL contacts with a single exposure. EUV simplifies the MOL flow compared to a traditional multi-patterning scheme, according to the paper.
The companies also devised a novel metallization layer called “M0” in the MOL scheme. “An M0 interconnect has been introduced to give more freedom regarding the MOL contact design and relieve the congestion in BEOL routing,” according to the paper.
On top of that, the MOL contacts are filled with cobalt, a move that reduces line resistance by more than 50%, the paper says.
This scheme faces some challenges, however. “The reliability performance of cobalt needs to be studied further,” UMC’s Liu said.
And as before, the insertion of EUV depends on whether the technology is ready and economical. “The state of EUV technology is much better than a year ago or two years ago,” said Aki Fujimura, chief executive of D2S. “The question is whether ‘much better’ is good enough for production.”
BEOL bottom blues
Meanwhile, following the MOL steps, the device then moves to the BEOL, which involves the formation of the interconnects on top of the MOL layers. Typically, a chip has 9 to 12 interconnect layers. Each layer, which has a wiring scheme, is connected to another layer with vias.
For years, the industry has used copper as the conductive metal in advanced logic interconnects. To devise the copper wiring schemes, chipmakers use a dual damascene process.
In this flow, a low-k dielectric material is first deposited on the surface. Based on a carbon doped oxide material, low-k films are used to isolate or insulate one part of the device from another. The films also reduce parasitic capacitance in the interconnects.
Low-k films are characterized by a dielectric constant or “k value.” Today’s low-k films have a “k value” of about 2.5 or 2.6. At one time the goal was to reduce the “k value” to about 2.2, which would further reduce the parasitic capacitance. But as chipmakers attempted to go to ultra low-k films at 2.2 and below, they found that these delicate low-k materials are prone to damage during the process and packaging flows.
So chipmakers are sticking with films at 2.6 or so. “Ultra low-k adoption has been slow with many integration issues coming up as we increase porosity,” said Mohith Verghese, director of global product marketing at ASM International. “This has driven the industry to look at alternatives, such as air gaps, lower-k etch stops and diffusion barriers.”
In fact, the industry is moving toward air gaps. Intel’s 14nm finFET process implements air gaps at two layers—MT4 and MT6. Air gaps bring the k-value down to its theoretical limit of 1.0.
But while air gaps lower the capacitance, they also add cost to the process. So air gaps will be implemented in some but not all chip designs. “Implementation will depend on product requirements and ROI,” said Mehul Naik, a principal member of the technical staff at Applied Materials.
Meanwhile, after the low-k film is deposited, the next step is to pattern the vias and trenches on the film. Metal lines are also patterned on the film. For patterning, chipmakers use immersion/multi-patterning.
The structure is etched, forming a via and trench. Then, inside the structure, a thin barrier layer (tantalum nitride) and liner layer (tantalum) are deposited. But at advanced nodes, the liner/barrier film is taking up too much room. So starting at 20nm, some began to replace tantalum with cobalt for the liner. Cobalt reduces the thickness of the liner. The barrier layer remains a tantalum nitride material.
Finally, the via/trench structure is filled with copper using electrochemical deposition. The process is repeated multiple times at each layer, thereby creating a copper wiring scheme.
But at 7nm, the BEOL process becomes unwieldy. One of challenges is to pattern the via/trench structure and metal lines on the first and second metal layers of the BEOL. Those layers, referred to as metal one (M1) and metal two (M2), are the smallest and most critical levels.
There are several ways to address the problem. Imec recently devised a patterning solution for a 42nm-pitch M1 layer and a 32nm-pitch M2 layer. In the process, the metal lines are formed using SAQP. Then the lines undergo a single EUV blocking or cut step.
Imec’s process provides a 20% wafer cost reduction over the immersion-only approach. “You could also use triple patterning immersion for the blocks, but that is very difficult and expensive,” said Greg McIntyre, director of the Advanced Patterning Department at Imec. “The alternate to this SAQP/block process is to just print the whole pattern in one show with single-print EUV. This would be preferred for cost reasons, but 32nm-pitch logic is not yet feasible with EUV single-print, due to stochastics, process windows and other factors.”
A copper replacement?
Besides EUV and a cobalt contacts, the industry is gearing up for the next big innovation for the BEOL—a replacement for copper.
Cobalt is emerging as a replacement candidate for copper at 5nm or sooner, at least for some but not all layers. “That could represent a sweeping change in the industry,” said G. Dan Hutcheson, chief executive of VLSI Research. “(Applied’s work) is very interesting. I am really impressed with it because everyone has been talking about trying to come up with a material to replace copper. Gold doesn’t work. Some have thrown aluminum back (at trailing-edge nodes).”
When will cobalt interconnects happen? “We are talking about beyond 10nm. 7nm is mostly locked down now,” Hutcheson said.
As stated above, the problem is that the via/trench structure is shrinking at each node. As a result, the volume of copper in this structure is decreasing. In effect, the copper wire is becoming thinner.
As the wire CDs scale below 30nm, the copper line resistivity is expected to dramatically increase, due to electron scattering and other factors. “Copper wire resistance actually increases as the wire gets smaller and smaller,” Applied’s Naik said in a blog. “And this degrades the performance significantly.”
At 5nm or so, Applied Materials sees a path of replacing copper with cobalt for some of the smaller wires or local interconnects in the lower levels. Copper would still be used for the thicker wires.
Cobalt is a higher resistive material than copper. But at certain dimensions, cobalt may show a lower resistance than copper. “Cobalt, on the other hand, has a mean free path that’s about four times lower than that of copper. What this means is that cobalt wire can be scaled down much further than a copper wire without a significant increase in electron scattering. In other words, cobalt becomes attractive as a copper replacement at CDs below 10 to 12nm,” Naik said.
For this, Applied has devised a cobalt fill flow for these layers. First, a thin liner material based on titanium nitride is deposited in the trench/via using atomic layer deposition. Then, a PECVD process at <250°C is used to fill the interconnect structures with cobalt, according to a paper from Applied Materials.
All told, Applied’s cobalt fill process demonstrated a gap fill without voids for a 10nm trench with a 20:1 aspect ratio, according to the paper.
Others are keeping a close eye on the technology. “Cobalt is one of the emerging materials,” Lam’s Pan said. “For certain structures and designs, it offers benefits of lower resistance or improved electromigration. We are seeing active development and adoption of cobalt for certain layers, and electroplating of cobalt is a cost-effective solution.”
There are other candidates besides cobalt in R&D. Moreover, the industry is also exploring other materials for the BEOL, such as ruthenium for the liner and manganese for the barrier.
But the industry doesn’t make changes overnight. Chipmakers tend to extend the current solutions as far as possible before moving to a new scheme. “Many considerations are involved when developing a new material or new application, such as ease of integration, reliability, interaction with upstream processes/materials, contamination, cost and scalability,” Pan said.