Interest in on-package heterogeneous integration (HI) has grown substantially in recent years. HI offers computing and communications devices enhanced functionality, faster time to market and silicon yield resiliency.
The package is the ideal heterogeneous integration platform because it provides short, power efficient, high bandwidth connections between components in a compact form factor. HI itself is not a new idea and a number of examples of on-package heterogeneous integration can be found in the past.
However, interest has grown recently because of product performance requirements for high data bandwidth between on-package components. Also, there is clear recognition that not all silicon IP can be optimized on a single fab process, and the package has become the platform of choice for heterogeneous integration.
In response, a number of innovative packaging technologies, such as EMIB, CoWoS and WLFO, have emerged creating excitement in the packaging community. These technologies provide extremely high wiring densities needed to achieve power efficient, high bandwidth interconnects. They open up new architectural possibilities for product and system architects to optimize system performance. This is truly an exciting time to be involved in packaging, assembly and test of HI devices
The trend towards increasing adoption of heterogeneous integration in mobile computing, automotive, high performance computing, medical devices, aerospace, defense and other demanding applications will continue. System-in-Package (SIP) architectures that integrate digital, analog, RF, optical and discrete devices for the high-performance, low-power, low-cost products of the future, are of great interest. These SIP technologies require a focused effort on feature size reduction to enable form-factor and component density scaling.
Planar and 3D architectures will be utilized. Efficient power delivery and enhanced thermal management will be needed to enable the successful evolution of these SIP architectures. SIP CAD flows that support of efficient heterogeneous design and verification will be essential.
Standardizing interfaces and protocols for MCP interconnect towards plug and play interoperability will go a long way in making SIP architectures successful. In addition, testing these complex systems in package is not a trivial task. Silicon architects and test engineers need to plan ahead to enable self-test circuitry, known good die, and combined analog, digital, RF & optical test flows. Without careful planning, compound yields on HI SIPs can ruin the viability of a product.
Heterogeneous integration of many diverse components from different sources brings unique design, process, materials, test, reliability, equipment and security challenges. Delivering cost/performance optimized SIP designs requires collaboration across multiple disciplines and an underlying roadmap that drives a shared vision, common terminology, and complementary design and process frameworks.
— Ravi Mahajan is an Intel Fellow for high density interconnect pathfinding. He is also a Fellow of IEEE and a Fellow of the American Society for Mechanical Engineers (ASME).