BY CHRISTOPHER NASH, NEW PRODUCT DEVELOPMENT MANAGER, INDIUM CORPORATION
Experiencing soldering defects? Need help with your SMT electronics assembly process? You’re not alone. Voiding is one of the electronics assembly’s longest and more troublesome challenges.
There are many factors to consider when working to reduce voiding – but where to start? Statistical tools, like the Ishikawa Diagram, help map out a process and provide an excellent visual aid that helps show the potential defect causes and the effects the process variables can have. These diagrams are often used to help discover the root cause of an issue by understanding all of the variables that could be causing it.
Figure 1 shows an Ishikawa Diagram for QFN/large ground plane voids that was developed to assist a customer that needed to reduce voiding under QFNs and DPAKs. This chart helped to identify the variables that could have been contributing to the observed large voiding percentages. Even though thousands of variables can affect a single process, and even though any diagram could be wildly complex, it is best to start with the most common sources. In this customer’s particular scenario, stencil design alterations – including stencil thickness and aperture design – helped reduce voiding.
In any Design Of Experiment (DOE) it is always important to change one variable at a time and to document your work so that you know if, and to what degree, each change affects the process. Also, if the change causes a negative impact on the process, your documented work will allow you to go back to the previous settings.
The following are any number of variables that can be analyzed and optimized to reduce voiding.
Stencil Design can have a tremendous effect on the voiding levels under Bottom-Terminated Components (BTC). See Figure 2. The amount of solder paste deposited on the board, and where the solder paste is deposited, can make the difference between 5-10% voiding and 40-60% voiding. It is important to consider these effects before designing your stencil and aperture patterns.
Countless studies and trials have shown that stencil thickness is one of the most critical factors to consider. Typically, a thicker stencil will yield less voiding. When the standoff of a particular component is higher (due to a thicker solder paste deposit from the use of a thicker stencil), the flux volatiles have more room to outgas and escape confinement under the component.
Studies show a statistical difference between a 4-mil thick stencil and a 5-mil thick stencil . In all cases, the 5-mil stencil has delivered better voiding performance. But, what would happen if a 6-mil or a 7-mil stencil was used? Typically a 6- or 7-mil stencil will result in too low of an area ratio for the paste to print properly through the apertures. For this reason, and a few others, it is often not feasible to use a thicker stencil. However, in some cases, there is a point where a thicker stencil will actually yield worse voiding.
Maximizing solder paste volume and height can be accomplished through avenues other than increasing the stencil thickness. Transfer efficiency is the percentage of the volume of the solder paste deposit divided by the volume of the aperture. Improving the transfer efficiency of the solder paste, through the stencil to the board, can also affect the volume and height of solder paste deposit, thus improving solder paste voiding performance under QFN components.
The stencil quality, stencil metal composition, age, wear, and stencil coating materials such as nano-coating, can all have a tremendous effect on the transfer efficiency of the solder paste. Not all stencil suppliers have the same stencil quality. Some stencils may have apertures that are incorrectly sized, cut in the wrong location, or skewed. If the apertures don’t correctly match up to the pads, the solder paste won’t properly transfer to the board with maximum volume and minimal variation.
The metal that the stencil is cut out of can also play a role in the transfer efficiency of the solder paste. Some metals have a lower surface tension than others, making it easier for the solder paste to transfer effectively. The same low surface tension benefit can be realized through the use of some nano-coating materials. The age of the stencil typically has a direct correlation to the wear of the stencil. If the stencil is worn or damaged, apertures may be coined, or rounded out, affecting how the paste will transfer through the stencil.
Aperture design is one more area that should be considered to reduce voiding under bottom-terminated components. Many of the component suppliers have aperture recommendations listed in the component’s data sheet. These recommendations are typically a good starting point, but changes in the windowpane size, shape, number of windowpane grills, and the size and shape of the windowpane grills can potentially reduce solder voids further.
Each component is different and, therefore, there is not a one-size-fits-all solution for aperture design. More windowpane apertures are typically better than less. Thinner windowpane grills are typically better than thicker. But, much like the stencil thickness, there will be a point where too many windowpanes and too thin a windowpane grill will start to increase voiding. See Figure 3. Is a rectangular shape better than a square or a circle or an oval? Each component is going react slightly different, so it is important to do some research and, possibly, some trials before production to see what performs the best in your process.
PCB Surface Finish Metallizations
There is a correlation between voiding percentages and different PCB surface finish metallizations. ENIG, Immersion Sn, and Organic Solderability Preservative (OSP) tend to be the most common PCB surface finishes in today’s Surface Mount Technology (SMT) industry. When comparing the voiding percentages of these three popular board metallizations under bottom-terminated components typically ENIG will produce the lowest level of voiding, followed by Immersion Sn, and then OSP.
There are different OSP versions available commercially, depending on where the boards are sourced from. Some OSP finishes may deliver better voiding performance than others. Unfortunately these differences can only be determined by trial and error.
Likewise, not all board houses have the same overall quality. Therefore, solder voiding performance will likely vary from one board house to another. It is important to choose the right board metallization for the application at the design stage in order to minimize the potential for voiding under BTCs.
Condition of the Boards
The age and storage condition of the boards also plays a role in voiding levels. An aged surface finish will oxidize unless stored in an oxygen-deprived environment. Oxidation is cleaned by the solder flux. A thicker oxide layer can make the cleaning process more challenging. It is possible that the flux may not fully clean portions of a heavily oxidized board pad/metallization, impairing solder wetting. Voiding caused by a wetting deficiency will be the typical result.
Virgin PCBs are often stored in nitrogen dry boxes to protect them from oxidation, but these storage boxes also protect the boards from moisture. If the boards are exposed to humid air they can absorb moisture which could create solder voids during the reflow process when the moisture transforms to a gas. If the gas does not escape the solder joint before solidification, a void will form.
The manufacturing environment is often overlooked as a root cause of issues and defects in electronics manufacturing assembly processes. It can be an easily identifiable starting point for determining the root cause of a solder paste viscosity issue. However, for voiding under bottom-terminated components, environmental conditions are frequently disregarded or forgotten about.
This is especially the case in lower-cost manufacturing operations, where the cost of implementing controlled HVAC systems and process controls is not monetarily feasible. Temperature and humidity variations outside the optimal range can wreak havoc on assembly materials like solder pastes, conformal coatings, glues, potting materials, fluxes, and underfills. In a scenario where the objective is to reduce voiding under a Bottom-Terminated Components (BTC), the temperature and humidity can certainly play a role. For example, if the temperature in the manufacturing environment is too high, the viscosity of the solder paste could decrease, causing slumping to occur prior to reflow. We have seen a similar scenario from the effect of stencil design/thickness: an increase in the component standoff tends to decrease BTC voiding. Conversely, if the solder paste slumps and the standoff between the board and the component is decreased, the voiding percentages under the component may increase.
Higher temperatures and prolonged exposure times can also speed up the oxidation process of the solder paste. Increased oxidation levels can increase voiding percentages. Poor storage and handling procedures, excessive time on the stencil, and/or prolonged room-temperature storage can affect both oxidation and viscosity characteristics of the solder paste.
Different geographies can also have an effect on BTC voiding. Some solder pastes, especially water-soluble solder pastes, may perform differently depending on the time of year. Winter months tend to be dryer and cooler than summer months in much of USA and Europe. These conditions can vary greatly from a place like Malaysia where it is hot and humid all year round. Thus, varying voiding results have even been observed in controlled experiments with identical setups with different geographic locations and altitudes.
The simplest things, that are often take for granted, can have a big effect.
Solder Paste Formulas
Solder paste is roughly 50% flux vehicle and 50% solder powder by volume, and, typically, 88-90% metal by weight (depending on the alloy and application). When it comes to voiding, the biggest difference between any solder pastes is the flux vehicle. There are many different flux vehicle options on the market; no-clean, water-soluble, and RMA. These formulations, all designed to meet different requirements and challenges, vary significantly. Consequently, some solder pastes perform better, with regard to voiding, than others.
The greater truth, and the reason why engineers are needed, is that voiding is not the only issue that a process engineer manages. Solder paste performance must also be considered with regard to: fine feature printing, high-warpage components, Non-Wet-Opens (NWO) and Head-In-Pillow (HiP) mitigation or better yet elimination, high Electro-Chemical Migration (ECM) reliability performance, and In Circuit Test (ICT) first-pass yields. In other words, there is not one single solution to solve the comprehensive list of challenges that manufacturers face on a daily basis.
Digging into solder paste concerns even further – there are factors that have a secondary effect on voiding, such as; viscosity, metal load, alloy, and metal mesh size (particle size distribution). Some examples are:
• Higher viscosity materials tend to void more than lower viscosity materials. This situation can be visualized by imagining a scenario where air bubbles trying to escape from honey versus air bubbles trying to escape from water.
• Metal load affects the viscosity of the material and, therefore, affects the BTC voiding performance.
• Alloy type affects wetting energy. Pb-free materials are not as straightforward as they once were when SAC305 was the definitive choice of many assemblers. We now have SAC405, SAC305, SAC105, low-Ag options for cost savings, and SAC alloys with dopants to increase solder joint reliability. The wetting energy, or the wetting force, of the alloy can have a dramatic effect on voiding performance. In essence, the higher the wetting energy the better the resultant BTC voiding results.
• Particle size distribution can also have an effect on voiding.
It is important to consider all aspects and characteristics of a solder paste simultaneously when determining how to reduce voiding in large ground plane component assembly, such as BTCs.
Printed Circuit Board (PCB) Design
PCB design can have a tremendous effect on BTC voiding. Vias in the thermal pads are often added in the board to aid in heat dissipation. Vias can be filled or buried, each would reduce voiding as compared to unfiled vias. Unfortunately, it is often too costly to fill the vias. Although through-hole vias may provide a channel for flux volatiles to escape, the size and shape of the via may increase BTC voiding.
In certain instances where large through-hole vias are present in the thermal ground pads, voiding is increased. In this scenario, the solder paste on the ground pad tends to wick down into the via during reflow. This results in reduced standoff height, which makes it harder for the flux volatiles to outgas properly causing increased BTC voiding.
Many PCB designs do not have vias. In these scenarios, the pad size and shape, along with the ratio between the board pad and the component pad has more of an effect on the BTC voiding. These variables can also effect designs with thermal pads with vias. If the thermal pad on the board is larger than the component thermal pad, the solder paste may wet out on the pad more, reducing the standoff of the component and increasing BTC voiding.
There are some designs that introduce solder mask on the pads to control standoff, reduce the size of the pad, or provide an outgassing channel. These designs can aid in the reduction of BTC voiding if designed properly for the specific component and application.
The Reflow Profile
Other than the solder paste flux vehicle chemistry, the reflow profile is the second most critical aspect of the PCB manufacturing process that will help reduce BTC voiding. Every aspect of the reflow profile is important, therefore the optimization process may take some time to dial in for the specific application and components.
The ramp rate and the time from ambient temperature to peak temperature can have an effect on how much and how quickly the flux volatiles will outgas. A faster ramp rate will typically volatilize the flux solvent more rapidly, reducing the amount that is present during the liquidus stage of the profile. This approach can also be prolonged with a flat soak period, though a linear ramp rate will often work the best. If a soak profile is used, the temperature of the soak can have an effect on the volatilization of the flux solvents as well. Typically, a soak zone just below the liquidus point of the alloy is used with modern flux chemistries, whereas in the past, the soak started around 150˚C and had a more gradual ramp to liquidus.
The Time Above Liquidus (TAL) and the peak temperature also have an effect. The longer the solder is molten the more time the flux volatiles have to escape the molten solder. However, this is a balancing act – more time will also allow for more volatiles to outgas into the molten solder, potentially increasing voiding. Time and temperature also play a role in the wetting speed and wetting force of the solder. Typically the more time the solder has to wet to the surface metallizations, the less voiding there will be. Increased temperature helps with wetting and typically reduces voiding.
The reflow atmosphere and the number of heating cycles that the assembly goes through also can affect the voiding performance. Is air or nitrogen being used? If nitrogen is being used what is the PPM level of oxygen in the oven? Typically nitrogen will aid with wetting by eliminating further oxidation to occur in the oven. Increased wetting will reduce voiding, so nitrogen atmospheres should present lower voiding percentages. This is not always the case, but remember there are many other variables in play.
BTC voiding – a long-term industry nuisance – and the ability to reduce it depend on a great number of process variables. Attention to detail through process optimization is just as critical for reduced voiding as the assembly materials. When you are looking to Avoid the Void™, remember: statistical tools, like the Ishikawa Diagram, are a methodical and reliable way to asses all the potential variables and aid in the discovery of the root cause of voiding.
1. Nash, C, Lasky, R.C., “Minimizing Voiding in SMT Assembly of BTCs,” SMTAI, Chicago, Sept 2016.
Area Ratio is the surface area of the stencil aperture opening divided by the area of the aperture side walls. It is typically desirable for the area ratio to be